
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Type II: Compensation when f CO > f ZERO, ESR
When the f CO is greater than f ESR , a Type II compensa-
V OUT_
C CF
tion network provides the necessary closed-loop com-
pensated response. The Type II compensation network
provides a midband compensating zero and a high-fre-
R 1
R F
C F
quency pole (see Figures 5a and 5b).
R F C F provides the midband zero f MID,ZERO , and
R F C CF provides the high-frequency pole, f HIGH,POLE .
Use the following procedure to calculate the compen-
R 2
FB_
V REF
COMP_
sation network components.
Calculate the f ESR and LC double pole, f LC :
Figure 5a. Type II Compensation Network
f ESR =
f LC ≈
1
2 π × ESR × C OUT
1
2 π × L × C OUT
GAIN
(dB)
( )
where C OUT is the regulator output capacitor and ESR
is the series resistance of C OUT . See the Output-
Capacitor Selection section for more information on cal-
culating C OUT and ESR.
Set the compensator’s leading zero, f Z1 , at or below the
1ST ASYMPTOTE
( ω R 1 C F ) -1
2ND ASYMPTOTE
R F -1
R I
3RD ASYMPTOTE
( ω R F C CF ) -1
filter’s resonant double-pole frequency from:
f Z1 ≤ f LC
Set the compensator’s high-frequency pole, f P1 , at or
1ST POLE
(AT ORIGIN)
1ST ZERO
(R F C F ) -1
2ND POLE
(R F C CF ) -1
ω (rad/sec)
f P1 ≤ SW
Gain E/A = F
Gain MOD = 4(V/V) ×
×
4 × ESR x V FB
R F 4 × ESR x V FB
2 π × f CO OUT_
× L x V
below one-half the switching frequency, f SW :
f
2
To maximize the compensator’s phase lead, set the
desired crossover frequency, f CO , equal to the geomet-
ric mean of the compensator’s leading zero, f Z1 , and
high-frequency pole, f P1 , as follows:
f CO = f Z1 × f P1
Select the feedback resistor, R F , in the range of 3.3k ?
to 30k ? .
Calculate the gain of the modulator (Gain MOD )—com-
prised of the regulator’s PWM, LC filter, feedback divider,
and associated circuitry—at the desired crossover fre-
quency, f CO , using the following equation:
ESR [m ? ] V FB [V]
( 2 π × f CO [kHz] × L[ μ H] ) V OUT_ [V]
where V FB is the 0.6V (typ) FB_ input-voltage set-point,
L is the value of the regulator inductor, ESR is the
Figure 5b. Type II Compensation Network Response
series resistance of the output capacitor, and V OUT_ is
the desired output voltage.
The gain of the error amplifier (Gain E/A ) in the midband
frequencies is:
R [k ? ]
R 1 [k ? ]
The total loop gain is the product of the modulator gain
and the error amplifier gain at f CO and should be set
equal to 1 as follows:
Gain MOD x Gain E/A = 1
So:
? R F ? ? ?
? ? ? ?
20 × log 10 ? R 1 ? + 20 × log 10 ?? 2 π × f CO × L x V OUT_ ?? = 0dB
× = 1
R 1
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